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<div class="title">CPU Section (New)<div class="ingroups"><a class="el" href="group__svd___format__1__1__gr.html">SVD Extension in Version 1.1</a></div></div>  </div>
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<p>The CPU section describes the processor included in the microcontroller device. This section is mandatory if the SVD file shall be used for the device header file generation.</p>
<pre>
<span class="opt">&lt;cpu&gt;</span>
    <span class="mand">&lt;name&gt;<em>cpuNameType</em>&lt;name&gt;
    &lt;revision&gt;<em>revisionType</em>&lt;revision&gt;
    &lt;endian&gt;<em>endianType</em>&lt;endian&gt;
    &lt;mpuPresent&gt;<em>xs:boolean</em>&lt;mpuPresent&gt;
    &lt;fpuPresent&gt;<em>xs:boolean</em>&lt;fpuPresent&gt;
    &lt;vtorPresent&gt;<em>xs:boolean</em>&lt;vtorPresent&gt;
    &lt;nvicPrioBits&gt;<em>scaledNonNegativeInteger</em>&lt;nvicPrioBits&gt;
    &lt;vendorSystickConfig&gt;<em>xs:boolean</em>&lt;vendorSystickConfig&gt;</span>
<span class="opt">&lt;/cpu&gt;</span>
</pre><table  class="cmtable" summary="CPU Section Elements">
<tr>
<th nowrap="nowrap">Element Name </th><th>Description </th><th>Type </th><th>Occurrence  </th></tr>
<tr>
<td>name </td><td>The predefined tokens are:<ul>
<li><span class="XML-Token">CM0</span>: ARM Cortex-M0</li>
<li><span class="XML-Token">CM0PLUS</span>: ARM Cortex-M0+</li>
<li><span class="XML-Token">CM3</span>: ARM Cortex-M3</li>
<li><span class="XML-Token">CM4</span>: ARM Cortex-M4</li>
<li><span class="XML-Token">SC000</span>: ARM Secure Core SC000</li>
<li><span class="XML-Token">SC300</span>: ARM Secure Core SC300</li>
<li><span class="XML-Token">other</span>: other processor architectures  </li>
</ul>
</td><td>cpuNameType  </td><td>1..1   </td></tr>
<tr>
<td>revisionType  </td><td>Defines the HW revision of the processor. The defined version format is <span class="XML-Token">r<em>N</em>p<em>M</em></span> (N,M = [0 - 9]).  </td><td>revisionType </td><td>1..1   </td></tr>
<tr>
<td>endian  </td><td>Defines the endianess of the processor being one of:<ul>
<li><span class="XML-Token">little</span>: little endian memory (least significant byte gets allocated at the lowest address).</li>
<li><span class="XML-Token">big</span>: byte invariant big endian data organization (most significant byte gets allocated at the lowest address).</li>
<li><span class="XML-Token">selectable</span>: little and big endian are configurable for the device and become active after the next reset.</li>
<li><span class="XML-Token">other</span>: the endianess is neither little nor big endian.  </li>
</ul>
</td><td>endianType  </td><td>1..1   </td></tr>
<tr>
<td>mpuPresent  </td><td>Indicates that the processor is equipped with a memory protection unit (MPU). This tag is either set to <span class="XML-Token">true</span> or <span class="XML-Token">false</span>, <span class="XML-Token">1</span> or <span class="XML-Token">0</span>. </td><td>boolean  </td><td>1..1   </td></tr>
<tr>
<td>fpuPresent  </td><td>Indicates that the processor is equipped with a hardware floating point unit (FPU). Cortex-M4 is the only available Cortex-M processor with an optional FPU. This tag is either set to <span class="XML-Token">true</span> or <span class="XML-Token">false</span>, <span class="XML-Token">1</span> or <span class="XML-Token">0</span>. </td><td>boolean  </td><td>1..1   </td></tr>
<tr>
<td>vtorPresent  </td><td>This is an optional flag used for the Cortex-M0+ based devices only. It indicates whether the Vector Table Offset Register (VTOR) is implemented in the Cortex-M0+ device or not. This tag is either set to <span class="XML-Token">true</span> or <span class="XML-Token">false</span>, <span class="XML-Token">1</span> or <span class="XML-Token">0</span>. If it is not specified VTOR is assumed to be present. </td><td>boolean  </td><td>1..1   </td></tr>
<tr>
<td>nvicPrioBits  </td><td>Defines the number of bits that are available in the Nested Vectored Interrupt Controller (NVIC) for configuring the priority. </td><td>scaledNonNegativeInteger  </td><td>1..1   </td></tr>
<tr>
<td>vendorSystickConfig </td><td>Indicates whether the processor implements a vendor-specific System Tick Timer. If <span class="XML-Token">false</span>, then the ARM defined System Tick Timer is available. If <span class="XML-Token">true</span>, then a vendor-specific System Tick Timer must be implemented. This tag is either set to <span class="XML-Token">true</span> or <span class="XML-Token">false</span>, <span class="XML-Token">1</span> or <span class="XML-Token">0</span>. </td><td>boolean  </td><td>1..1   </td></tr>
</table>
<h1><a class="anchor" id="cpuSection_ex"></a>
Example:</h1>
<div class="fragment"><div class="line">...</div>
<div class="line">&lt;cpu&gt;</div>
<div class="line">    &lt;name&gt;CM4&lt;/name&gt; </div>
<div class="line">    &lt;revision&gt;r0p0&lt;/revision&gt;</div>
<div class="line">    &lt;endian&gt;little&lt;/endian&gt;</div>
<div class="line">    &lt;mpuPresent&gt;<span class="keyword">true</span>&lt;/mpuPresent&gt;</div>
<div class="line">    &lt;fpuPresent&gt;<span class="keyword">true</span>&lt;/fpuPresent&gt;</div>
<div class="line">    &lt;nvicPrioBits&gt;4&lt;/nvicPrioBits&gt;</div>
<div class="line">    &lt;vendorSystickConfig&gt;<span class="keyword">false</span>&lt;/vendorSystickConfig&gt; </div>
<div class="line">&lt;/cpu&gt;  </div>
<div class="line">...</div>
</div><!-- fragment --><p>This example describes a Cortex-M4 core of HW revision r0p0, with fixed little endian memory scheme, including Memory Protection Unit and hardware Floating Point Unit. The Nested Vectored Interrupt Controller uses 4 bits for configuring the priority of an interrupt. It is equipped with the standard System Tick Timer as defined by ARM. </p>
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